Design Automation of Low Dropout Voltage Regulators: A General Approach

Analog design is an inherently intricate process comprising many trade-offs; as a result, it iterative time-consuming operation. A low dropout voltage regulator (LDO) example of such analog blocks that involve myriad trade-offs. In this paper, we present automated procedure for LDOs using precomputed look-up tables (LUTs) and the gm/ID methodology. Using symbolic solver LUTs, database LDO contains one million points generated in few seconds. The provides visualization space exploration trade-offs across different corners load currents. provided to demonstrate 40 nm technology results are verified Cadence Spectre simulator. approach holistic sense uses accurate capture small signal model complexities, incorporates LUTs calculation large solution parameters, fast because simulator loop scenario omitted, almost all specifications incorporated.